1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of flowable boron-contained silicon glass films by using a High Density Plasma Chemical Vapor Deposition (HDP-CVD) technique with gas mixtures containing silane or its derivatives, necessary doping precursors, and oxygen.
2. Description of the Prior Art
In the fabrication of devices such as semiconductor devices, a variety of material layers are sequentially formed and processed on the substrate. For the purpose of this disclosure, the substrate includes a bulk material such as semiconductor, e.g., silicon, body, and if present, various regions of materials such as dielectric materials, conducting materials, metallic materials, and/or semiconductor materials. One of the material regions utilized in this fabrication procedure includes silicon oxide based materials, i.e., materials generally represented by the common formula SiOn, where n=xcx9c2, including doped silicon oxide films, containing an additional doping element such as boron, phosphorus, and their mixtures, as well as fluorine, with total dopant content depending on the purpose of film application in the device. Below the common term xe2x80x9csilicate glass filmxe2x80x9d is used to characterize silicate glass films.
In ULSI device technology, thin films, including silicon dioxide based films, are created on the substrates using a Chemical Vapor Deposition (CVD) technique that assumes a deposition of the solid state material (glass) on the hot substrate from the gas mixture of precursors and oxidizer. It is realized at different conditions, basically at atmospheric pressure (APCVD), low pressure (LPCVD), subatmospheric pressure (SACVD) reduced pressure, and with plasma excitation of gas mixtures (PECVD). A variety of silicon compounds and doping precursors have been used for film deposition. However, most common compounds are hydrides such as silane, fluorinated silane derivatives, phosphine, diborane, tetraethylortosilicate (TEOS), organic ethers of boric and phosphoric acids such as methylphosphates, ethylborates, etc. Oxygen has been commonly used as an oxidizer until recently when its mixture with ozone has been found to improve deposition process characteristics. Normally, film deposition during this process takes place with a constant deposition rate in the range of 0.1-10 Kxc3x85 per minute depending on the method used and its particular conditions.
A silicate glass film is often deposited on a substrate 101 (FIG. 1) having a plurality of steps, e.g., conducting steps. A feature of CVD processes is a non-conformal step coverage of growing film 103 on the step 102 on the device substrate 101 that schematically shown in FIG. 1, namely the film thickness on the top of structure is always higher as compared to the bottom and side wall thickness. Step coverage is normally expressed as a ratio of film thickness on the structure side wall xe2x80x9cSxe2x80x9d to the thickness on the structure top xe2x80x9cTxe2x80x9d, as shown in FIG. 1. This ratio is different for different deposition processes as well as for current structures and is in the range of 15-90%.
Among other techniques used in semiconductor processing, silicon oxide based films (including fluorosilicate and phosphosilicate glass films) have been deposited during the last few years using a modified Plasma Enhanced Chemical Vapor Deposition (PECVD) called a High Density Plasma Chemical Vapor Deposition (HDP-CVD) technique. This technique assumes simultaneous deposition and sputtering of depositing films in order to improve gap-fill capability, as shown schematically in FIG. 2. FIG. 2 shows steps 102 formed on a semiconductor substrate 101. The silicon oxide or silicon glass film 103 is deposited over the steps 102. Material species are shown 104 on the surface of the film. Ionized Ar molecules 105 bombard the surface of the film resulting in sputtered and redeposited material 106 and vaporized material species 107. The method of chemical vapor deposition of silicon oxide and doped silicon glass films at High Density Plasma conditions (HDP-CVD) with silane-oxygen based gas mixtures is used in semiconductor manufacturing mostly for sub-quarter micron Ultra Large Scale Integrated (ULSI) circuit device applications. This method is used for deposition of silicon oxide, or frequently known as undoped silicon glass (USG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), i.e. films which typically should not be subjected to thermal treatment at elevated temperatures. In the case of doped films, the dopant precursor, such as phosphine PH3, for example, is added to the silane-oxygen mixture. Also, organic/inorganic silane derivatives, such as tetrafluorosilane SiF4 or difluorosilane SiH2F2 are used either alone or in a mixture with silane.
Silicate glass regions are utilized as insulating/passivating layers, as an electrical insulation between conducting layers, e.g., polysilicon or metal layers. Films of undoped silicon oxide are used also as a liner or as a cap layer either under or on the doped silicon oxide layers, respectively, to limit unacceptable dopant migration during subsequent processing. Tightening of device design rules leads to more complicated device structures with small gaps 201 (FIG. 3A) between neighboring elements. As a result of CVD non-conformal film growth on the top, side walls and bottom of such device structures that are shown schematically as a thinner film on the structure side wall 202 as compared to that thickness on the top of structure (this is due to the deposition kinetic features and diffusion limitation in small gaps), voids 203 (FIG. 3B) form inside structure elements. These voids have normally a keyhole shape that is valid for CVD methods for all current types of films. The voids are more or less pronounced depending on particular deposition conditions.
The reason for void formation is a common non-conformal glass film growth during film deposition that is shown schematically in FIG. 4A-C for different deposition techniques currently used in device manufacturing, such as LPCVD (FIG. 4A), APCVD (FIG. 4B), and PECVD (FIG. 4C). As can be seen in FIG. 4A, reduced pressure provides normally better step coverage, however, it normally means a lower deposition rate. Atmospheric pressure at certain conditions can cause even imperfection of film integrity in the bottom corners of structures 205, as shown in FIG. 4B. The last technique, being a part of HDP-CVD technique, provides the worst known case of step coverage, mostly below 50% even for single device steps, as well as imperfection of film integrity in the bottom corners 205 and the very specific xe2x80x9cbread-loafxe2x80x9d shape of the growing film 206, as shown in FIG. 4C.
Among the CVD.process features, void size is strongly dependent on the structure parameters, such as structure shape, size of gaps between device elements (G) and structure height (H) which are normally combined to express structure complexity as an aspect ratio (AR=H/G)), as shown as an example in FIG. 4A. To characterize an ability of film to fill narrow gaps between device elements, a term xe2x80x9cgap-fill capabilityxe2x80x9d is normally used and structures without any imperfection between device elements seen in cross-section of real structures using scanning electron microscopy techniques, are normally called xe2x80x9cvoid-freexe2x80x9d. The void problem is significantly affected by structure shape being much more pronounced for structures with re-entrant gap shape, as shown schematically in terms of step coverage in FIG. 5 followed by the structure with vertical side walls. The best void-free gap-fill is normally achieved with structure tapering, however this approach is not applicable for all devices. FIG. 5 shows a re-entrant gap shape 120, a vertical gap shape 122, and a tapered gap shape 124.
The problem of film integrity and void formation at HDP-CVD processes (below the common term xe2x80x9cvoidsxe2x80x9d is used for both types of film structure imperfection) in different types of as-deposited HDP-CVD films have been found and analyzed recently, see for instance: [Ref.1]: R. Conti, L. Economikos, G. D. Parasouliotis, et al. xe2x80x9cProcessing Methods to Fill High Aspect Ratio Gaps Without Premature Construction,xe2x80x9d Proceedings of Fifth Dielectrics for ULSI Multilevel Int.Conf. (DUMIC), (1999), p. 201 and [Ref.2]: J. Yota, A. Joshi, C. Nguyen et al. xe2x80x9cExtendibility of ICP High-Density Plasma CVD for Use as Intermetal dielectric and Passivation Layers for 0.18 um Technology,xe2x80x9d Proceedings of Fifth Dielectrics for ULSI Multilevel Int.Conf. (DUMIC), (1999), p.71.
The reason for void formation under HDP-CVD conditions is normally explained as a result of redeposition of the film on the nearest surfaces caused by etch/sputtering of the film with argon bombardment from the top edges of structure steps, as shown in FIG. 2. This effect is shown in progress in FIG. 6. Continuous deposition with etch/sputtering causes the formation of film 103 on the steps 102 (shown in FIG. 6A), followed by void nucleation and formation 207 at the smallest spacings, as shown in FIG. 6B and FIG. 6C, followed by thin seam formation at the certain critical spacing (Gcritical) and critical aspect ratios (ARcritical) 208. At the same time, a void-free film forms at a certain gap spacing, which is larger than critical, and aspect ratio, which is less than critical, as shown in FIG. 2B, 209, that eventually leads to the void-free gap-fill when the full film thickness is achieved, as shown in FIG. 6C.
Detailed analysis of HDP-CVD gap-fill capability for an example of structures with vertical side wall steps, mostly desired for ULSI applications, has been performed in [Ref.3]: V. Vassillev, C. Lin, D. Fung et al. xe2x80x9cProperties and Gap fill Capability of HDP-PSG Films for 0.18 um Device Applications and Beyond,xe2x80x9d Proceedings of Fifth Dielectrics for ULSI Multilevel Int.Conf. (DUMIC), (1999), p.235, for he above mentioned film types and two main ranges of the HDP-CVD deposition temperature, namely, less than about 400xc2x0 C and higher than about 500xc2x0 C. Eventually, HDP-CVD gap-fill capability limitations for the commonly used deposition conditions can be quantitatively described by a simple equation (1):
ARcriticalxe2x89xa6kxc3x97Gcritical,xe2x80x83xe2x80x83(1)
where the values of coefficient k have been found to be about 13.3 xcexcmxe2x88x921 and 20.1 xcexcmxe2x88x921 for high and low temperature processes, respectively. To reduce void formation effects in HDP-CVD, e.g. to enhance gap-fill capability of the HDP-CVD technique, the following approaches have been considered recently:
a) a decrease of the etch (sputtering) component to deposition ratio (below xe2x80x9cE/D ratioxe2x80x9d) and decrease of process pressure. This helps to reduce an impact of film sputtering and, therefore, re-deposition. However, these measures cause an undesirable decrease of HDP-CVD process productivity as well as a necessity to enhance pump productivity.
b) structure rounding, as described in [Ref. 3]. In fact, such rounding allows much better HDP-CVD gap-fill capability using the same process conditions, including pressure, power, and etch to deposition ratio. However, this approach is not applicable for all ULSI device structure elements.
Thus, for device structures with vertical side walls the following common numbers of void-free as-deposited film gap-fill capability with different deposition techniques have been found, as shown in the Table 1, together with typical gap-fill requirements of sub-quarter micron ULSI logic device application. It is clear that all currently used methods do not allow achievement of void-free structures with tight parameters, which is known to be getting even tighter with further device development.
One of the major intrinsic properties of glasses, including silicon-based glasses, is an ability to soften, or to flow at enhanced temperatures. Applying this phenomenon to ULSI device application, it allows a planarization of a non-planar device surface (see FIG. 7A) using a thermal treatment of a non-planar as-deposited glass film which is able to soften at elevated temperatures above the temperature of its softening to form a planar film surface, as shown schematically in FIG. 7B. In semiconductor manufacturing, mostly in ULSI device technology, just a few options of silicate glasses have been used, mostly phosphosilicate and borophosphosilicate glasses (PSG and BPSG). Along with the surface planarization at elevated temperatures, film softening at elevated temperatures allows elimination of voids. Most effective for void elimination are high temperatures providing significant lowering of glass viscosity. Shape of gaps is also very important for the gap-fill after thermal treatment: the best gap-fill can be achieved with tapered device structures that generally shows a trend that better as-deposited gap-fill leads to the best gap-fill after any comparable thermal treatment.
Thermal anneal conditions are very important for ULSI technology. Development of silicide-based gates in the latest ULSI devices with sub-quarter micron design rules has enhanced a necessity to lower the post silicide thermal budget to lower than about 800xc2x0 C. Such a low temperature is not sufficient enough to provide required glass softening and as a result of this, low thermal budget anneal conditions, such as low isothermal furnace anneal, or rapid thermal anneal at temperatures less than 800xc2x0 C., does not provide sufficient film flow. Thus, a problem of voids 301 in thermally treated silicate glass films, as shown in FIG. 7B, in device structures has arisen in device generations with design rules less than about 0.25 xcexcm, and, especially, in devices with less than 0.18 xcexcm design rules. Voids are undesirable because etching and dielectric properties will be non-uniform.
Phosphorus-contained films with very high phosphorus concentrations of about 10 wt. % are capable of flowing at temperatures above 1000xc2x0 C., but that temperature is not acceptable for modern device applications and beyond. Thus, the latest HDP-CVD PSG films are supposed to not flow at the low thermal budget conditions. Due to the low thermal budget requirements, boron-contained films, such as BPSG films, are considered to be more preferable for ULSI technology that is due to the effective decrease of softening temperature with the boron doping as compared to that of phosphorus. However, boron-contained BPSG films deposited at current APCVD, RPCVD and PECVD conditions do not allow sufficient enough as-deposited film gap-fill capability and, therefore, post thermal treatment gap-fill capability at low thermal budget conditions.
Thus, voids in device structures are not acceptable because of a worsening of device reliability. Therefore, it is very desirable to produce a good HDP-CVD film integrity and gap-fill capability. The prior art processes do not provide a silicon oxide layer that can satisfactorily fill gaps between the increasingly tight step features of new ULSI semiconductor devices without forming voids in between the conductor lines. Therefore, it is very desirable to produce glass films without any imperfection, such as voids inside dielectric material.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following.
U.S. Pat. No. 5,899,736 to Weigand et al teaches a phosphorus-doped HDP-CVD oxide film. U.S. Pat. No. 5,976,993 to Ravi et al teaches HDP-CVD silicon dioxide with reduced stress using biasing during deposition. U.S Pat. No. 5,776,834 to Avanzino et al teaches HDP-CVD silicon dioxide over a conformal TEOS layer where a void is purposefully created within the silicon dioxide layer in small gaps.
It is an object of the present invention to provide a method for fabrication of flowable boron-contained silicon class films by using a High Density Plasma Chemical Vapor Deposition (HDP-CVD) technique with gas mixtures containing silane or its derivatives, necessary doping precursors, and oxygen.
It is an object of the present invention to provide a method for fabricating a flowable boron-contained silicon class layer over a stepped substrate surface using HDP-CVD process that produces good integrity of film along the device steps and void-free structures. The invention""s xe2x80x9cboron-contained HDP-CVD glass filmxe2x80x9d process and preferred Invention""s process conditions are shown below n Table 2. The most critical parameters in the invention are dopants to silicon source mole ratio, sputtering to deposition ratio, and total pressure.
The invention has the following advantages: much better as compared to other deposition techniques: as deposited gap-fill capability at commonly used deposition conditions, such as process pressure, etch to deposition ratio, relatively high deposition rate and process productivity, good film quality, and very good film gap-fill after film thermal treatment at elevated temperatures. Besides, it is simply realized and there is no need to change chamber design.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by the reference to the latter portions of the specification and attached drawings.